Wafer Level Packaging/ Panel Level Packaging (WLP/ PLP)

Due to cost pressure in the semiconductor industry wafer or panel level packaging is a method of packaging an integreted circuit (IC) directly on the wafer or panel. It has large potential for further miniaturization, both in volume and in thickness. For high-troughput requirements high frequency eddy current technology characterizes sheet resistance, conductivity, thickness and homogeneity of metal layers.

Testing

Sheet resistance
Conductivity
Thickness
Homogeneity

Substrate types

Wafer
Glass
Plastics (molded compounds)

Common substrate sizes

410 mm x 515 mm
510 mm x 515 mm
500 mm x 500 mm
600 mm x 600 mm
650 mm x 650 mm

Typical layers

Processes

Plating
Sputtering

Further resources

SEMI MF673 — Test Method for Measuring Resistivity of Semiconductor Wafers or Sheet Resistance of Semiconductor Films with a Noncontact Eddy-Current Gauge
SEMI M59 — Terminology for Silicon Technology
SEMI MF81 — Test Method for Measuring Radial Resistivity Variation on Silicon Wafers
SEMI MF84 — Test Method for Measuring Resistivity of Silicon Wafers with an In-Line Four-Point Probe
SEMI MF374 — Test Method for Sheet Resistance of Silicon Epitaxial, Diffused, Polysilicon, and Ion-Implanted Layers Using an In-Line Four-Point Probe with the Single-Configuration Procedure
SEMI MF1527 — Guide for Application of Certified Reference Materials and Reference Wafers for Calibration and Control of Instruments for Measuring Resistivity of Silicon